Although IA64 provides a full 64 bit address space, not all implementations implement all 64 bits of it. This goes for other processors to; on the Alpha the minimum implemented bits is 48 (the same rules about sign extending VA's apply to Alpha too). This means that a virtual address may have a number of unimplemented bits in the middle of it; for example (taken from Mosberger, pg. 150)
+---> IMPL_VA_MSB
|
+------+----------------+---------------------------+
| VRN | unimplemented | implemented |
+------+----------------+---------------------------+
This leads to a large hole in the middle of the address space. The thing that leads to a hole in the middle is the extra rule that the unimplemented bits must be sign extended (i.e. made the same as) the most significant bit of the implemented address bits.
Mosberger uses full 64 bit addresses in the example so it is a little hard to conceptualise this gap, but it's easy if you imagine you only have a three bit machine. Bit 1 is like the VRN, Bit 2 is unimplemented, and Bit 3 is your implemented address bits.
The full address space of the three bit machine looks like
| Bit 1 | Bit 2 | Bit 3 |
| 1 | 1 | 1 |
| 1 | 1 | 0 |
| 1 | 0 | 1 |
| 1 | 0 | 0 |
| 0 | 1 | 1 |
| 0 | 1 | 0 |
| 0 | 0 | 1 |
| 0 | 0 | 0 |
Now, do another table with Bit 2 (the "unimplemented bit") sign extended from Bit 3
| Bit 1 | Bit 2 | Bit 3 |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
| 1 | 0 | 0 |
| 0 | 1 | 1 |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 0 | 0 | 0 |
Below, the unimplemented addresses are in bold. You can see if you just take Bit 1 and Bit 3, you end up with the entire two bit address space (i.e. 00,01,10,11) and a hole in the middle!
Bit 1
Bit 2
Bit 3
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
You can think of the addresses as aliased, since if you follow the rules you can only get to addresses in your two bit address space. However, you can of course not follow the rules and request from the processor a dodgey address; at that point it will raise an exception.